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Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation.

, , , , , , , , and . IRPS, page 1-4. IEEE, (2020)

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Interoperability for ITS: An Ontology of Learning Style Models., and . ITS, volume 7315 of Lecture Notes in Computer Science, page 671-672. Springer, (2012)A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant., , , and . IRPS, page 1-4. IEEE, (2019)Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event., , and . SoCC, page 109-114. IEEE, (2014)Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation., , , , , , , , and . IRPS, page 1-4. IEEE, (2020)Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp., , , , and . IRPS, page 1-5. IEEE, (2021)Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology., , , , , , , and . IRPS, page 1-4. IEEE, (2020)Investigation of diode triggered silicon control rectifier turn-on time during ESD events., , and . SoCC, page 175-178. IEEE, (2017)Latchup Analysis Using Emission Microscopy., , , , , , , , , and . Microelectron. Reliab., 43 (9-11): 1603-1608 (2003)Optical and Electrical Testing of Latchup in I/O Interface Circuits., , , , , , , and . ITC, page 236-245. IEEE Computer Society, (2003)ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies., , and . CICC, page 1-4. IEEE, (2020)