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Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor.

, , , , and . CICC, page 1-4. IEEE, (2014)

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Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor., , , , and . CICC, page 1-4. IEEE, (2014)A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology., , , , , , , , , and 1 other author(s). CICC, page 159-162. IEEE, (2003)Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICs., , , , , , , , , and 7 other author(s). CICC, page 559-566. IEEE, (2001)Resonant clock mega-mesh for the IBM z13TM., , , , , , , , , and 2 other author(s). VLSIC, page 322-. IEEE, (2015)Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Processes., , , and . VLSI Design, page 188-193. IEEE Computer Society, (2010)RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications., , , , , , , , , and . VLSI Design, page 194-199. IEEE Computer Society, (2010)Product applications and technology directions with SiGe BiCMOS., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 38 (9): 1471-1478 (2003)On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices., , , , , , , , , and 6 other author(s). DAC, page 724-727. ACM, (2003)Frequency-independent equivalent circuit model for on-chip spiral inductors., , , , , , , and . CICC, page 217-220. IEEE, (2002)Virtual de-embedding study for the accurate extraction of Fin FET gate resistance., , , , , , , , and . CICC, page 1-4. IEEE, (2014)