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Performance verification of high-performance ASICs using at-speed structural test., , , , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 247-252. ACM, (2006)Defect-Oriented Test for Ultra-Low DPM., и . Asian Test Symposium, стр. 455. IEEE Computer Society, (2005)A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization., , , и . DATE, стр. 11188-11190. IEEE Computer Society, (2003)Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking., и . DATE, стр. 652-657. European Design and Automation Association, Leuven, Belgium, (2006)Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters., , и . VTS, стр. 22-27. IEEE Computer Society, (1999)On the Use of k-tuples for SoC Test Schedule Representation., и . ITC, стр. 539-548. IEEE Computer Society, (2002)Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints., , , и . ITC, стр. 1159-1168. IEEE Computer Society, (2002)Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking., , и . VTS, стр. 46-51. IEEE Computer Society, (2006)Physically-Aware N-Detect Test., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (2): 308-321 (2012)Test cost reduction for SOCs using virtual TAMs and lagrange multipliers., , , и . DAC, стр. 738-743. ACM, (2003)