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Low cost at-speed testing using On-Product Clock Generation compatible with test compression.

, , , , , , , , и . ITC, стр. 724-733. IEEE Computer Society, (2010)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

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A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices., , и . VLSID, стр. 5-6. IEEE Computer Society, (2014)Probe point insertion for at-speed test., , и . VTS, стр. 223-228. IEEE Computer Society, (1992)Impact of high level functional constraints on testability., , и . VTS, стр. 309-312. IEEE Computer Society, (1993)Design for Testability Using Architectural Descriptions., , и . ITC, стр. 752-761. IEEE Computer Society, (1992)A Design For Test Perspective on I/O Management., , , и . ICCD, стр. 46-53. IEEE Computer Society, (1996)A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures., , , , , , и . NATW, стр. 43-48. IEEE, (2015)Advancing test compression to the physical dimension., , , , , , , , и . ITC, стр. 1-10. IEEE, (2017)Non-Scan Design-for-Testability Techniques for Sequential Circuits., , , и . DAC, стр. 236-241. ACM Press, (1993)Channel Masking Synthesis for Efficient On-Chip Test Compression., , и . ITC, стр. 452-461. IEEE Computer Society, (2004)