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Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number., , , , , , and . PDPTA, page 1775-1781. CSREA Press, (2003)Gradual write-barrier insertion into a Ruby interpreter.. ISMM, page 115-121. ACM, (2019)Implementation and Evaluation of a Thread Library for Multithreaded Architecture., , , , , , and . PDPTA, page 609-615. CSREA Press, (2003)A decentralized access control mechanism using authorization certificate for distributed file systems., and . ICITST, page 148-153. IEEE, (2011)Development of a Thread Scheduler for SMT Processor Architecture., , , , , , and . PDPTA, page 454-460. CSREA Press, (2005)Towards Reconfigurable Cache Memory for a Multithreaded Processor., , , , , , , , and . PDPTA, page 916-924. CSREA Press, (2006)A Model of Implementable SMT Processor on FPGA., , , , , , , , and . PDPTA, page 909-915. CSREA Press, (2006)Dynamic Allocation of Physical Register Banks for an SMT Processor., , , , , , , and . PDPTA, page 317-323. CSREA Press, (2004)A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture., , , , , , and . PDPTA, page 1669-1675. CSREA Press, (2003)A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation., , , , , , , and . PDPTA, page 447-453. CSREA Press, (2005)