( en | de | ru )

 

Disambiguation of "Jinguji, Akira"

Author of the publication

copydeleteadd this publication to your clipboard
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network.

, , , and . FPT, page 310-313. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Akira Hayashima

Akira Hori

Akira Satake

Akira Yasui

Akira Hayashima

 

Other publications of authors with the same name

An FPGA-based Fine Tuning Accelerator for a Sparse CNN., , , and . FPGA, page 186. ACM, (2019)Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs., , and . FCCM, page 229. IEEE, (2020)A Random Forest Using a Multi-valued Decision Diagram on an FPGA., , , and . ISMVL, page 266-271. IEEE Computer Society, (2017)R2CNN: Recurrent Residual Convolutional Neural Network on FPGA., , , and . FPGA, page 319. ACM, (2020)Fast Monocular Depth Estimation on an FPGA., , , , , and . IPDPS Workshops, page 143-146. IEEE, (2020)An acceleration of a random forest classification using Altera SDK for OpenCL., , , and . FPT, page 289-292. IEEE, (2016)Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA., , and . FPL, page 424-425. IEEE, (2019)A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference., , and . MCSoC, page 446-453. IEEE, (2023)A Multilayer Perceptron Training Accelerator using Systolic Array., , , and . APCCAS, page 77-80. IEEE, (2021)A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA., , , and . FPT, page 267-270. IEEE, (2019)