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RapidStream: Parallel Physical Implementation of FPGA HLS Designs.

L. Guo, P. Maidee, Y. Zhou, C. Lavin, J. Wang, Y. Chi, W. Qiao, A. Kaviani, Z. Zhang, and J. Cong. FPGA, page 1-12. ACM, (2022)

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Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Ying Chi

Other publications of authors with the same name

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.G. Dai, Y. Chi, Y. Wang, and H. Yang. FPGA, page 105-110. ACM, (2016)Extending High-Level Synthesis for Task-Parallel Programs.Y. Chi, L. Guo, Y. kyu Choi, J. Wang, and J. Cong. CoRR, (2020)RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.L. Guo, P. Maidee, Y. Zhou, C. Lavin, E. Hung, W. Li, J. Lau, W. Qiao, Y. Chi, L. Song and 4 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (4): 59:1-59:30 (December 2023)TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis.Y. Choi, Y. Chi, J. Lau, and J. Cong. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2423-2427 (July 2023)SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs.X. Tian, Z. Ye, A. Lu, L. Guo, Y. Chi, and Z. Fang. CoRR, (2022)TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.N. Prakriya, Y. Chi, S. Basalama, L. Song, and J. Cong. CoRR, (2023)NXgraph: An Efficient Graph Processing System on a Single Machine.Y. Chi, G. Dai, Y. Wang, G. Sun, G. Li, and H. Yang. CoRR, (2015)Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.L. Song, L. Guo, S. Basalama, Y. Chi, R. Lucas, and J. Cong. FPGA, page 247-258. ACM, (2023)HBM Connect: High-Performance HLS Interconnect for FPGA HBM.Y. kyu Choi, Y. Chi, W. Qiao, N. Samardzic, and J. Cong. FPGA, page 116-126. ACM, (2021)Extending High-Level Synthesis for Task-Parallel Programs.Y. Chi, L. Guo, J. Lau, Y. kyu Choi, J. Wang, and J. Cong. FCCM, page 204-213. IEEE, (2021)

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Disambiguation of "Chi, Yuze"

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RapidStream: Parallel Physical Implementation of FPGA HLS Designs.

Please choose a person to relate this publication to

Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Ying Chi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chi, Yuze"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RapidStream: Parallel Physical Implementation of FPGA HLS Designs.

Please choose a person to relate this publication to

Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Ying Chi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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RapidStream: Parallel Physical Implementation of FPGA HLS Designs.