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A Novel Approach for Testing Memories Using a Built-In Self Testing Technique., and . ITC, page 830-839. IEEE Computer Society, (1986)Identifying high variability speed-limiting paths under aging., , , and . LATS, page 1-6. IEEE, (2017)A low cost approach to calibrate on-chip thermal sensors., , , , and . ISQED, page 572-576. IEEE, (2011)Testable Design of Single-Output Sequential Machines Using Checking Experiments., and . IEEE Trans. Computers, 35 (7): 658-662 (1986)SEU tolerant SRAM cell., , , , and . ISQED, page 597-602. IEEE, (2011)Transient Fault Resilient QR Factorization on GPUs., , and . FTXS@HPDC, page 63-70. ACM, (2015)Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles., , and . GLOBECOM, IEEE, (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)