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A Novel ATPG Method for Capture Power Reduction during Scan Testing.

, , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)

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A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Design of High-Level Test Language for Digital LSI., , and . ITC, page 508-513. IEEE Computer Society, (1983)Design of testing circuit and test generation for built-in current testing., , and . Syst. Comput. Jpn., 24 (5): 73-82 (1993)Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs., , , and . VLSI Design, page 329-334. IEEE Computer Society, (2003)Low-capture-power test generation for scan-based at-speed testing., , , , , , and . ITC, page 10. IEEE Computer Society, (2005)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (1996)An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits., , and . Asian Test Symposium, page 22-. IEEE Computer Society, (1997)Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits., , and . Asian Test Symposium, page 121-126. IEEE Computer Society, (1999)IDDQ Current Dependency on Test Vectors and Bridging Resistance., , and . Asian Test Symposium, page 158-163. IEEE Computer Society, (1999)Resynthesis for sequential circuits designed with a specified initial state., , and . VTS, page 152-157. IEEE Computer Society, (1995)