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Disambiguation of "Garyfallou, Dimitrios"

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Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.

, , , , and . ACM Great Lakes Symposium on VLSI, page 77-83. ACM, (2022)

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Dimitrios Koulousakis

Dimitrios Papakostas

Dimitrios Papasotiriou

Dimitrios Repantis

Dimitrios Alexiadis

 

Other publications of authors with the same name

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance., , , , and . ACM Great Lakes Symposium on VLSI, page 77-83. ACM, (2022)A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects., , , and . SMACD, page 89-92. IEEE, (2019)Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures., , and . MOCAST, page 1-4. IEEE, (2018)A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s., , and . SMACD, page 209-212. IEEE, (2018)MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits., , , , , , , , , and 7 other author(s). CoRR, (2024)A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential., , , , and . ASP-DAC, page 1-6. ACM, (2023)Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential., , , , and . SMACD, page 1-4. IEEE, (2023)Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis., , , , , and . DFT, page 1-6. IEEE, (2023)EVT-based worst case delay estimation under process variation., , , and . DATE, page 1333-1338. IEEE, (2018)Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models., , , , and . ASP-DAC, page 773-778. ACM, (2021)