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Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.

, , , and . FPT, page 137-144. IEEE, (2005)

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Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse., , and . IRI, page 318-325. IEEE Systems, Man, and Cybernetics Society, (2005)On variable ordering of binary decision diagrams for the application of multi-level logic synthesis., , and . EURO-DAC, page 50-54. EEE Computer Society, (1991)Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition., , , and . IEEE Trans. Computers, 64 (6): 1579-1593 (2015)RTL datapath optimization using system-level transformations., , , and . ISQED, page 309-316. IEEE, (2014)Specification and formal verification of power gating in processors., and . ISQED, page 604-610. IEEE, (2014)Early case splitting and false path detection to improve high level ATPG techniques., and . ISCAS, page 1463-1466. IEEE, (2011)A small biped entertainment robot exploring attractive applications., , , , and . ICRA, page 471-476. IEEE, (2003)A new approach for selecting inputs of logic functions during debug., and . ISQED, page 166-173. IEEE, (2017)Multiple Error Diagnosis Based on Xlists., , , , and . DAC, page 660-665. ACM Press, (1999)Efficient Sum-to-One Subsets Algorithm for Logic Optimization., and . DAC, page 443-448. IEEE Computer Society Press, (1992)