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s Sensitivity, -41dB SIR and 174dB RX FoM in 22nm CMOS.

H. Bialek, M. Johnston, and A. Natarajan. ISSCC, page 474-475. IEEE, (2023)

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Kasyap Natarajan

Paruthiure Natarajan

Umeswaran Arunagirinathan

Natarajan Thiagarajan

Arupon Natarajan

Other publications of authors with the same name

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, J. Tierno, A. Babakhani, S. Yaldiz, A. Valdes-Garcia, B. Sadhu and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-Handling.A. Nagulu, S. Garikapati, M. Essawy, I. Kadota, T. Chen, A. Natarajan, G. Zussman, and H. Krishnaswamy. ISSCC, page 100-102. IEEE, (2021)9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS.J. Cheng, N. Qi, P. Chiang, and A. Natarajan. ISSCC, page 168-169. IEEE, (2014)A 20 μ W, 0.05mm2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing Systems.J. Kim, C. Votzke, S. Bose, A. Natarajan, and M. Johnston. CICC, page 1-2. IEEE, (2021)29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS.A. Ramachandran, A. Natarajan, and T. Anand. ISSCC, page 488-489. IEEE, (2017)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)NSDMiner: Automated discovery of Network Service Dependencies.A. Natarajan, P. Ning, Y. Liu, S. Jajodia, and S. Hutchinson. INFOCOM, page 2507-2515. IEEE, (2012)Indirect phase noise sensing for self-healing voltage controlled oscillators.S. Yaldiz, V. Calayir, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, and J. Tierno. CICC, page 1-4. IEEE, (2011)Integrated Phased Array Systems in Silicon.A. Hajimiri, H. Hashemi, A. Natarajan, X. Guan, and A. Komijani. Proc. IEEE, 93 (9): 1637-1655 (2005)A 0.4-to-0.95GHz Distributed N-Path Noise-Cancelling Ultra-Low-Power RX with Integrated Passives Achieving -85dBm/100kb/s Sensitivity, -41dB SIR and 174dB RX FoM in 22nm CMOS.H. Bialek, M. Johnston, and A. Natarajan. ISSCC, page 474-475. IEEE, (2023)

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Disambiguation of "Natarajan, Arun"