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A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology., , , , , and . CICC, page 1-4. IEEE, (2015)Analog/Mixed-Signal Layout Optimization using Optimal Well Taps., , , , , , , and . ISPD, page 159-166. ACM, (2022)Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (7): 1264-1277 (2008)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2012)Common-Centroid Layouts for Analog Circuits: Advantages and Limitations., , , , , , and . DATE, page 1224-1229. IEEE, (2021)Machine Learning Techniques in Analog Layout Automation., , , , , , , , , and 3 other author(s). ISPD, page 71-72. ACM, (2021)Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems., , , , and . ESTIMedia, page 135-140. IEEE Computer Society, (2005)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)SRAM parametric failure analysis., , , and . DAC, page 496-501. ACM, (2009)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement., , , , , , and . DATE, page 148-153. IEEE, (2022)