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Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack., , , , , , и . J. Electron. Test., 35 (6): 887-900 (2019)Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale., , , и . IEEE Des. Test Comput., 22 (4): 295-297 (2005)Hardware acceleration of feature detection and description algorithms on low-power embedded platforms., , , , и . FPL, стр. 1-9. IEEE, (2016)ABACUS: A technique for automated behavioral synthesis of approximate computing circuits., , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)CMOS dynamic power estimation based on collapsible current source transistor modeling., , , , , и . ISLPD, стр. 111-116. ACM, (1995)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs., , , , , , и . CODES+ISSS, стр. 39-48. ACM, (2011)Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation., , , , и . SPAA, стр. 297-308. ACM, (2019)Trends and Future Directions in Nano Structure Based Computing and Fabrication.. ICCD, стр. 522-527. IEEE, (2006)Fetch Halting on Critical Load Misses., , , , и . ICCD, стр. 244-249. IEEE Computer Society, (2004)RESTA: a robust and extendable symbolic timing analysis tool., , , и . ACM Great Lakes Symposium on VLSI, стр. 407-412. ACM, (2004)