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Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.

, , , and . IEEE Des. Test Comput., 22 (4): 295-297 (2005)

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Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , and . Embedded Systems and Applications, page 139-143. CSREA Press, (2003)A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation., , , , , and . IEEE Trans. Computers, 63 (6): 1336-1350 (2014)A defect/error-tolerant nanosystem architecture for DSP., , and . JETC, 5 (4): 18:1-18:22 (2009)A model for computing and energy dissipation of molecular QCA devices and circuits., , and . JETC, 3 (4): 3:1-3:30 (2008)Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment., , , , , , , and . IEEE Trans. Instrumentation and Measurement, 52 (6): 1749-1755 (2003)Modeling and analysis of fault tolerant multistage interconnection networks., , and . IEEE Trans. Instrumentation and Measurement, 52 (5): 1509-1519 (2003)Design and Analysis of Approximate Compressors for Multiplication., , , and . IEEE Trans. Computers, 64 (4): 984-994 (2015)On a Novel Self-Test Approach to Digital Testing., and . Comput. J., 30 (3): 258-267 (1987)A Technique for Reconfiguring Two Dimensional VLSI Arrays., , and . RTSS, page 44-53. IEEE Computer Society, (1987)Testing Layered Interconnection Networks., , , and . IEEE Trans. Computers, 53 (6): 710-722 (2004)