Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip., , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)REDRESS: Generating Compressed Models for Edge Inference Using Tsetlin Machines., , , , , , and . IEEE Trans. Pattern Anal. Mach. Intell., 45 (9): 11152-11168 (September 2023)Low-Latency Asynchronous Logic Design for Inference at the Edge., , , and . CoRR, (2020)Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools., , and . DATE, page 1715-1724. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path., , , and . NEWCAS, page 1-4. IEEE, (2016)Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets., , , and . PATMOS, page 69-74. IEEE, (2019)Synthesis of SI Circuits from Burst-Mode Specifications., , , , and . DATE, page 366-369. IEEE, (2021)Low-Latency Asynchronous Logic Design for Inference at the Edge., , , and . DATE, page 370-373. IEEE, (2021)Automated Synthesis of Asynchronous Tsetlin Machines on FPGA., , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Asynchronous design, Quo Vadis?. DDECS, page 3. IEEE Computer Society, (2010)