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Safe and efficient supervised memory systems., , , and . HPCA, page 369-380. IEEE Computer Society, (2011)Ring Oscillator Clocks and Margins., , , , and . ASYNC, page 19-26. IEEE Computer Society, (2016)Version management alternatives for hardware transactional memory., , and . MEDEA@PACT, page 69-76. ACM, (2008)A Dynamically Adaptable Hardware Transactional Memory., , and . MICRO, page 27-38. IEEE Computer Society, (2010)Architectural support for high-performing hardware transactional memory systems.. Polytechnic University of Catalonia, Spain, (2011)Speculative hardware/software co-designed floating-point multiply-add fusion., , , , , , and . ASPLOS, page 623-638. ACM, (2014)Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip., , , , , , , , , and 23 other author(s). HCS, page 1-23. IEEE, (2021)FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery., , and . PACT, page 293-302. IEEE Computer Society, (2009)Reactive clocks with variability-tracking jitter., , , , , , and . ICCD, page 511-518. IEEE Computer Society, (2015)