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Disambiguation of "Fujii, Shuso"

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A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.

, , , , , , , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1745-1752 (2010)

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Fumio Fujii

Fumio Fujii

Fumio Fujii

Tadahiko Fujii

Fumio Fujii

 

Other publications of authors with the same name

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , and 23 other author(s). ISSCC, page 464-465. IEEE, (2009)A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1745-1752 (2010)A 286 mm2 256 Mb DRAM with ×32 both-ends DQ., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 31 (4): 567-574 (1996)Design of a 128-mb SOI DRAM using the floating body cell (FBC)., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 41 (1): 135-145 (2006)An embedded DRAM technology for high-performance NAND flash memories., , , , , and . ISSCC, page 504-505. IEEE, (2011)A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance., , , , and . IEEE J. Solid State Circuits, 46 (2): 530-536 (2011)A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM., , , , , , , , , and 9 other author(s). ISSCC, page 262-263. IEEE, (2010)A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes., , , , , , , , , and 23 other author(s). IEEE J. Solid State Circuits, 45 (1): 142-152 (2010)Flexible test mode approach for 256-Mb DRAM., , , , , , , , , and . IEEE J. Solid State Circuits, 32 (10): 1525-1534 (1997)Fault-tolerant designs for 256 Mb DRAM., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 31 (4): 558-566 (1996)