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Improving Cache Performance in a Multiprocessor Environment., and . PDPTA, page 413-422. CSREA Press, (1995)Classification and Performance Evaluation of Instruction Buffering Techniques., , , and . ISCA, page 150-159. ACM, (1991)Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories., , , and . ICPP (1), page 212-219. CRC Press, (1994)Design and VLSI implementation of an access processor for a decoupled architecture., , , and . Microprocess. Microsystems, 16 (5): 237-247 (1992)A global synchronization network for a non-deterministic simulation architecture., and . WSC, page 1460-1469. WSC, (1999)0-7803-5780-9.Program Balance and Its Impact on High Performance RISC Architectures., , , and . HPCA, page 370-379. IEEE Computer Society, (1995)Structured Data Access Mechanisms for a Decoupled Computer Architecture., , and . ICPP (2), page 285-289. CRC Press, (1994)Performance Analysis of an Address Generation Coprocessor., , and . ICPP (1), page 136-143. CRC Press, (1991)A Reconfigurable Multiprocessor., and . ICPP, page 649-651. IEEE Computer Society Press, (1985)Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module., , and . ISCA, page 236-245. ACM, (1992)