( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.

, , , , и . IEEE J. Solid State Circuits, 43 (9): 2109-2119 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Hiroyuki Tan

Hiroyuki Kobayashi

Hiroyuki Takada

Hiroyuki Isobe

Hiroyuki Okamuro

 

Другие публикации лиц с тем же именем

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , и . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies.. IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 763-774 (2010)17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme., , , , , и . ISSCC, стр. 1-3. IEEE, (2015)Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs., и . SoCC, стр. 318-323. IEEE, (2014)Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs., и . LATS, стр. 1-6. IEEE Computer Society, (2015)A Method and Language for Constructing Multiagent Systems., и . ISMIS, том 1932 из Lecture Notes in Computer Science, стр. 619-628. Springer, (2000)A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme., , , , , , и . IEEE J. Solid State Circuits, 52 (9): 2498-2514 (2017)A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme., , , и . CICC, стр. 233-236. IEEE, (2007)Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions., и . ICICDT, стр. 33-36. IEEE, (2013)Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation., и . VLSI-SoC, стр. 1-6. IEEE, (2014)