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Disambiguation of "Chang, Meng-Fan"

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A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme.

, , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2498-2514 (2017)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matching. TU München, (2009)
 

Other publications of authors with the same name

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices., , , , , , , , , and 3 other author(s). VLSI Circuits, page 166-. IEEE, (2019)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse., , , , , , , , , and 1 other author(s). ISSCC, page 234-236. IEEE, (2020)