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Statistical Delay Fault Coverage and Defect Level for Delay Faults.

, , and . ITC, page 492-499. IEEE Computer Society, (1988)

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Delay Testing Quality in Timing-Optimized Designs., , , and . ITC, page 897-905. IEEE Computer Society, (1991)Fast seed computation for reseeding shift register in test pattern compression., , and . ICCAD, page 76-81. ACM / IEEE Computer Society, (2002)Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects., , , , , , and . ITC, page 1041-1050. IEEE Computer Society, (2003)Tester retargetable patterns., and . ITC, page 721-727. IEEE Computer Society, (2001)Changing the Scan Enable during Shift., , , , , and . VTS, page 73-78. IEEE Computer Society, (2004)IDDQ Test: Sensitivity Analysis of Scaling., , , , and . ITC, page 786-792. IEEE Computer Society, (1996)On Efficiently and Reliably Achieving Low Defective Part Levels., , and . ITC, page 616-625. IEEE Computer Society, (1995)Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture., , , and . DATE, page 10110-10115. IEEE Computer Society, (2003)Directed-Binary Search in Logic BIST Diagnostics., , and . DATE, page 1121. IEEE Computer Society, (2002)Design for Testability: The Path to Deep Submicron.. Asian Test Symposium, IEEE Computer Society, (2005)