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Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification., , , и . IEEE Des. Test, 34 (5): 5-6 (2017)A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor., , и . CICC, стр. 71-74. IEEE, (2000)Design Optimization Based on Diagnosis Techniques., , и . LATW, стр. 244-249. IEEE, (2000)ATPG Driven Logic Synthesis for Delay and Power Minimization., , и . LATW, стр. 96-99. IEEE, (2001)Automated Test Model Generation from Switch Level Custom Circuits., , , и . Asian Test Symposium, стр. 184-189. IEEE Computer Society, (2003)LEAF: A System Level Leakage-Aware Floorplanner for SoCs., , , , и . ASP-DAC, стр. 274-279. IEEE Computer Society, (2007)On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults., , и . ITC, стр. 398-406. IEEE Computer Society, (2002)Minimizing outlier delay test cost in the presence of systematic variability., , , и . ITC, стр. 1-10. IEEE Computer Society, (2009)Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained., , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Forward prediction based on wafer sort data - A case study., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2011)