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Not All Features Are Equal: Discovering Essential Features for Preserving Prediction Privacy., , , , , and . WWW, page 669-680. ACM / IW3C2, (2021)EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security., , , , , and . MICRO, page 1218-1236. IEEE, (2022)Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX., , , and . USENIX Security Symposium, page 51-67. USENIX Association, (2017)Swivel: Hardening WebAssembly against Spectre., , , , , , , , , and 1 other author(s). USENIX Security Symposium, page 1433-1450. USENIX Association, (2021)Limitations of Cache Prefetching on a Bus-Based Multiprocessor., and . ISCA, page 278-288. ACM, (1993)Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling., , and . ISCA, page 408-419. IEEE Computer Society, (2005)Multithreaded Execution Architecture and Compilation., and . HPCA, page 321. IEEE Computer Society, (1999)Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading., , and . PACT, page 313-324. IEEE Computer Society, (2009)Power-sensitive multithreaded architecture., , and . ICCD, page 17-24. IEEE Computer Society, (2012)Inter-socket victim cacheing for platform power reduction., , and . ICCD, page 509-514. IEEE Computer Society, (2010)