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8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications.

, , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem., , , , and . PATMOS, page 56-63. IEEE, (2016)A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy., , , and . ISLPED, page 1-6. IEEE, (2019)A Fokker-Planck Solver to Model MTJ Stochasticity., , and . ESSDERC, page 263-266. IEEE, (2021)A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing., , , , and . ESSCIRC, page 1-4. IEEE, (2019)27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power., , , , , , , , , and 1 other author(s). ISSCC, page 422-424. IEEE, (2020)A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller., , , , , and . IEEE J. Solid State Circuits, 56 (2): 601-611 (2021)Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library., , , and . ISVLSI, page 19-24. IEEE Computer Society, (2017)Evaluation and analysis of single-phase clock flip-flops for NTV applications., , , , , and . PATMOS, page 1-6. IEEE, (2017)8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications., , , , , and . ISSCC, page 1-3. IEEE, (2015)A Compact Model for Scalable MTJ Simulation., , , and . CoRR, (2021)