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Serial/Parallel architectures for area-efficient vector multiplication.

, and . ICASSP, page 539-542. IEEE, (1987)

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The Parallel Performance of a Groundwater Flow Code on the Cray T3D., , , and . PPSC, page 131-136. SIAM, (1995)Advanced Serial-Data Computation., and . J. Parallel Distributed Comput., 5 (3): 228-249 (1988)Integrating ns-3 model construction, description, preprocessing, execution, and visualization., , , , , , , and . SimuTools, page 176-181. ICST/ACM, (2013)Pushing the envelope in distributed ns-3 simulations: one billion nodes., , , , and . WNS3, page 67-74. ACM, (2015)Full-span structural compilation of DSP hardware., , , , , , and . ICASSP, page 495-498. IEEE, (1987)Serial/Parallel architectures for area-efficient vector multiplication., and . ICASSP, page 539-542. IEEE, (1987)Techniques to increase the computational throughput of bit-serial architectures., , and . ICASSP, page 543-546. IEEE, (1987)Synthesis of area-efficient VLSI architectures for vector and matrix multiplication., and . IEEE Symposium on Computer Arithmetic, page 13-20. IEEE Computer Society, (1987)The Design and Evolution of Zipcode., , , , and . Parallel Comput., 20 (4): 565-596 (1994)A comparison of micro-DSP and Silicon compiler implementations of a polyphase network filter bank., , , , , and . ICASSP, page 2207-2210. IEEE, (1986)