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Disambiguation of "Fujiwara, Hideo"

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Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

The Complexity of Fault Detection Problems for Combinational Logic Circuits., and . IEEE Trans. Computers, 31 (6): 555-560 (1982)Test pattern selection to optimize delay test quality with a limited size of test set., , , , and . European Test Symposium, page 260. IEEE Computer Society, (2010)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , and . WDAG, volume 1320 of Lecture Notes in Computer Science, page 290-304. Springer, (1997)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , and . DISC, volume 5805 of Lecture Notes in Computer Science, page 172-173. Springer, (2009)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)A Test Generation Method Based on k-Cycle Testing for Finite State Machines., , and . IOLTS, page 232-235. IEEE, (2019)Fast false path identification based on functional unsensitizability using RTL information., , , and . ASP-DAC, page 660-665. IEEE, (2009)Secure scan design using shift register equivalents against differential behavior attack., , and . ASP-DAC, page 818-823. IEEE, (2011)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)