( en | de | ru )

 

Disambiguation of "Zimmer, Brian"

Author of the publication

copydeleteadd this publication to your clipboard
Simba: scaling deep-learning inference with chiplet-based architecture.

, , , , , , , , , , , , , , , , and . Commun. ACM, 64 (6): 107-116 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

Brian Alexander

 

Other publications of authors with the same name

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm., , , , , , , , and . IEEE J. Solid State Circuits, 58 (4): 1129-1141 (2023)A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (1): 43-54 (2019)AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies., , , , , , , , , and . ISPD, page 175-183. ACM, (2022)Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM., , , , , and . ESSDERC, page 98-101. IEEE, (2014)Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor., , , and . IEEE J. Solid State Circuits, 52 (10): 2589-2600 (2017)Simba: scaling deep-learning inference with chiplet-based architecture., , , , , , , , , and 7 other author(s). Commun. ACM, 64 (6): 107-116 (2021)Resilient Design Techniques for Improving Cache Energy Efficiency.. University of California, Berkeley, USA, (2015)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture., , , , , , , , , and 7 other author(s). MICRO, page 14-27. ACM, (2019)6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links., , , , , , , , , and 1 other author(s). ISSCC, page 126-128. IEEE, (2020)A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (2): 557-567 (2016)