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Test Compression Improvement with EDT Channel Sharing in SoC Designs., , , , , , , and . NATW, page 22-31. IEEE, (2014)X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 147-159 (2008)Efficient Test Compression Configuration Selection., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2323-2336 (2022)X-Press Compactor for 1000x Reduction of Test Data., , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs., , , , , , , , , and 3 other author(s). ITC, page 1-10. IEEE, (2020)Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels., , , , , , , , and . ITC-Asia, page 130-135. IEEE, (2020)Dynamic channel allocation for higher EDT compression in SoC designs., , , , , and . ITC, page 265-274. IEEE Computer Society, (2010)Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains., , , and . ITC, page 114-123. IEEE Computer Society, (2010)Realizing High Test Quality Goals with Smart Test Resource Usage., , , , , , , and . ITC, page 525-533. IEEE Computer Society, (2004)EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism., , , , , , and . ITC, page 1-9. IEEE Computer Society, (2011)