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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi, W. Wang, S. Mueller, S. Ben-Yehuda, J. Bonanno, N. Cao, R. Casatuta, C. Chen, M. Cohen, O. Erez, T. Fox, G. Gristede, H. Haynie, V. Ivanov, S. Koswatta, S. Lo, M. Lutz, G. Maier, A. Mesh, Y. Nustov, S. Rider, M. Schaal, M. Scheuermann, X. Sun, N. Wang, F. Yee, C. Zhou, V. Shah, B. Curran, V. Srinivasan, P. Lu, S. Shukla, K. Gopalakrishnan, and L. Chang. VLSI Circuits, page 1-2. IEEE, (2020)

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Wallace Kwesi Bruce-Tamakloe

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The IBM eServer z990 floating-point unit.G. Gerwig, H. Wetter, E. Schwarz, J. Haess, C. Krygowski, B. Fleischer, and M. Kroener. IBM J. Res. Dev., 48 (3-4): 311-322 (2004)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, V. Vaden, and A. Goyal. ISSCC, page 1728-1734. IEEE, (2006)Exponent monitoring for low-cost concurrent error detection in FPU control logic.M. Maniatakos, Y. Makris, P. Kudva, and B. Fleischer. VTS, page 235-240. IEEE Computer Society, (2011)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference.A. Agrawal, B. Fleischer, S. Mueller, X. Sun, N. Wang, J. Choi, and K. Gopalakrishnan. ARITH, page 92-95. IEEE, (2019)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)64-bit prefix adders: Power-efficient topologies and design solutions.C. Zhou, B. Fleischer, M. Gschwind, and R. Puri. CICC, page 179-182. IEEE, (2009)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran and 44 other author(s). ISCA, page 153-166. IEEE, (2021)

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Disambiguation of "Fleischer, Bruce M."

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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

Please choose a person to relate this publication to

Wallace Kwesi Bruce-Tamakloe

Cecil Bruce-Boye

Beate Maria Bruce-Micah

Annette Bruce

Regina Beatrice Bruce-Micah

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Fleischer, Bruce M."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

Please choose a person to relate this publication to

Wallace Kwesi Bruce-Tamakloe

Cecil Bruce-Boye

Beate Maria Bruce-Micah

Annette Bruce

Regina Beatrice Bruce-Micah

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.