( en | de | ru )

 

Disambiguation of "Narayanan, Vijaykrishnan"

Author of the publication

copydeleteadd this publication to your clipboard
Communication-efficient k-Means for Edge-based Machine Learning.

, , , , , , , and . CoRR, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

 

Other publications of authors with the same name

Width minimization in the Single-Electron Transistor array synthesis., , , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Process-Variation-Aware Adaptive Cache Architecture and Management., , , , , , and . IEEE Trans. Computers, 58 (7): 865-877 (2009)A scalable architecture for multi-class visual object detection., , , , and . FPL, page 1-8. IEEE, (2015)A reconfigurable platform for the design and verification of domain-specific accelerators., , , and . ASP-DAC, page 108-113. IEEE, (2012)Going Vertical: The Future of Electronics.. IEEE Micro, 39 (6): 6-7 (2019)A hardware accelerated multilevel visual classifier for embedded visual-assist systems., , , , and . ICCAD, page 96-100. IEEE, (2014)Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies., , , , and . IJDSN, 5 (3): 209-223 (2009)Design considerations for databus charge recovery., , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 104-106 (2001)Managing Leakage Energy in Cache Hierarchies., , , , , , and . J. Instruction-Level Parallelism, (2003)A clock power model to evaluate impact of architectural and technology optimizations., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 844-855 (2002)