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Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator.

, , and . DAC, page 535-540. IEEE Computer Society Press, (1990)

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Compaction of ATPG-generated test sequences for sequential circuits., , , , and . ICCAD, page 382-385. IEEE Computer Society, (1988)PROOFS: a fast, memory-efficient sequential circuit fault simulator., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (2): 198-207 (1992)HITEC: a test generation package for sequential circuits., and . EURO-DAC, page 214-218. EEE Computer Society, (1991)Methods for Reducing Events in Sequential Circuit Fault Simulation., , and . ICCAD, page 546-549. IEEE Computer Society, (1991)Test compaction for sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (2): 260-267 (1992)A genetic algorithm framework for test generation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1034-1044 (1997)Techniques for sequential circuit automatic test generation. University of Illinois Urbana-Champaign, USA, (1991)Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator., , and . DAC, page 535-540. IEEE Computer Society Press, (1990)Sequential Circuit Test Generation in a Genetic Algorithm Framework., , , and . DAC, page 698-704. ACM Press, (1994)