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Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator.

, , and . DAC, page 535-540. IEEE Computer Society Press, (1990)

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Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors., , and . DAC, page 155-159. ACM, (1991)ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation., , and . DAC, page 717-721. ACM Press, (1994)Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories., , and . DAC, page 689-694. IEEE Computer Society Press / ACM, (1987)A Functional-Level Test Generation Methodology Using Two-level Representations., and . DAC, page 722-725. ACM Press, (1989)Compiler Directed Memory Management Policy For Numerical Programs., and . SOSP, page 97-106. ACM, (1985)Operating System Review 19(5).Test compaction for sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (2): 260-267 (1992)A genetic algorithm framework for test generation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1034-1044 (1997)Improving a nonenumerative method to estimate path delay fault coverage., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 759-762 (1997)Hierarchical test generation under architectural level functional constraints., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (9): 1144-1151 (1996)Design of Test Pattern Generators for Built-In Test., , and . ITC, page 315-319. IEEE Computer Society, (1984)