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Bridging defects resistance in the metal layer of a CMOS process., , и . J. Electron. Test., 8 (1): 35-46 (1996)On Maximizing the Coverage of Catastrophic and Parametric Faults., и . J. Electron. Test., 16 (3): 251-258 (2000)Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (8): 1386-1395 (2016)Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1911-1922 (2011)Experimental Characterization of CMOS Interconnect Open Defects., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 123-136 (2008)IDDQ testing: state of the art and future trends., , , , и . Integr., 26 (1-2): 167-196 (1998)A Discussion on Test Pattern Generation for FPGA - Implemented Circuits., , , , и . J. Electron. Test., 17 (3-4): 283-290 (2001)An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family., , , и . J. Electron. Test., 16 (3): 289-299 (2000)Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours., , , и . J. Electron. Test., 20 (2): 143-153 (2004)Minimizing the Number of Test Configurations for Different FPGA Families., , , и . Asian Test Symposium, стр. 363-368. IEEE Computer Society, (1999)