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A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices.

W. Khwa, Y. Chiu, C. Jhang, S. Huang, C. Lee, T. Wen, F. Chang, S. Yu, T. Lee, и M. Chang. ISSCC, стр. 1-3. IEEE, (2022)

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Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matchingM. Zhang. TU München, (2009)

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang и 7 other автор(ы). ISSCC, стр. 494-496. IEEE, (2018)Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices.K. Tang, W. Wei, Z. Yeh, T. Hsu, Y. Chiu, C. Xue, Y. Kuo, T. Wen, M. Ho, C. Lo и 3 other автор(ы). VLSI Circuits, стр. 166-. IEEE, (2019)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.M. Chang, C. Lin, A. Lee, C. Kuo, G. Yang, H. Tsai, T. Chen, S. Sheu, P. Tseng, H. Lee и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.X. Si, W. Khwa, J. Chen, J. Li, X. Sun, R. Liu, S. Yu, H. Yamauchi, Q. Li, и M. Chang. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (11): 4172-4185 (2019)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel.T. Hsu, Y. Chen, J. Wu, W. Ting, C. Wang, C. Yeh, S. Sie, Y. Chen, R. Liu, C. Lo и 3 other автор(ы). ISSCC, стр. 110-112. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices.T. Chang, Y. Chiu, C. Lee, J. Hung, K. Chang, C. Xue, S. Wu, H. Kao, P. Chen, H. Huang и 2 other автор(ы). ISSCC, стр. 224-226. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.J. Yue, Z. Yuan, X. Feng, Y. He, Z. Zhang, X. Si, R. Liu, M. Chang, X. Li, H. Yang и 1 other автор(ы). ISSCC, стр. 234-236. IEEE, (2020)A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme.H. Hsu, T. Wen, W. Huang, W. Khwa, Y. Lo, C. Jhang, Y. Chin, Y. Chen, C. Lo, R. Liu и 5 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 116-127 (января 2024)A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.B. Lin, Y. Pang, B. Gao, J. Tang, D. Wu, T. Chang, W. Lin, X. Sun, S. Yu, M. Chang и 2 other автор(ы). IEEE J. Solid State Circuits, 56 (5): 1641-1650 (2021)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.A. Lele, M. Chang, S. Spetalnick, B. Crafton, S. Konno, Z. Wan, A. Bhat, W. Khwa, Y. Chih, M. Chang и 1 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 52-64 (января 2024)

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Please choose a person to relate this publication to

Fan Chen Meng

Meng-Chang Liu

Meng Meng

Meng Meng Liang

Meng Zhang

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