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Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.

, , , , , , , , , , и . ITC, стр. 1-10. IEEE, (2020)

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Randa Kassab

Hisham Kassab

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Islam Yassin-Kassab

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Другие публикации лиц с тем же именем

Test Compression Improvement with EDT Channel Sharing in SoC Designs., , , , , , , и . NATW, стр. 22-31. IEEE, (2014)Efficient Test Compression Configuration Selection., , , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2323-2336 (2022)X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 147-159 (2008)Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs., , , , , , , , , и 3 other автор(ы). ITC, стр. 1-10. IEEE, (2020)X-Press Compactor for 1000x Reduction of Test Data., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2006)Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains., , , и . ITC, стр. 114-123. IEEE Computer Society, (2010)Realizing High Test Quality Goals with Smart Test Resource Usage., , , , , , , и . ITC, стр. 525-533. IEEE Computer Society, (2004)EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism., , , , , , и . ITC, стр. 1-9. IEEE Computer Society, (2011)Dynamic channel allocation for higher EDT compression in SoC designs., , , , , и . ITC, стр. 265-274. IEEE Computer Society, (2010)Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels., , , , , , , , и . ITC-Asia, стр. 130-135. IEEE, (2020)