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S. Lee, J. Lee, I. Park, J. Park, S. Yun, M. Kim, J. Lee, M. Kim, K. Lee, T. Kim, B. Cho, D. Cho, S. Yun, J. Im, H. Yim, K. Kang, S. Jeon, S. Jo, Y. Ahn, S. Joe, S. Kim, D. kyun Woo, J. Park, H. Park, Y. Kim, J. Park, Y. Choi, M. Hirano, J. Ihm, B. Jeong, S. Lee, M. Kim, H. Lee, S. Seo, H. Jeon, C. ho Kim, H. Kim, J. Kim, Y. Yim, H. Kim, D. Byeon, H. Yang, K. Park, K. Kyung, and J. Choi. ISSCC, page 138-139. IEEE, (2016)

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Wonmin Byeon

Boseon Byeon

In-Deok Seok

Joon-Weon Seok

Dae-Ho Cho

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A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.D. Na, J. Lee, S. Lee, H. Cho, J. Lee, M. Yang, E. Song, A. Kavala, T. Kim, D. Jang and 12 other author(s). IEEE J. Solid State Circuits, 56 (4): 1129-1140 (2021)Cell Operation Technologies to Overcome Scale-down Issues in 3D NAND Flash Memory.W. Kim, D. Byeon, S. Joe, J. Lee, and J. Song. ICEIC, page 298-299. IEEE, (2022)High-performance 1-Gb-NAND flash memory with 0.12-μm technology.J. Lee, H. Im, D. Byeon, K. Lee, D. Chae, K. Lee, S. Hwang, S. Lee, Y. Lim, J. Lee and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1502-1509 (2002)7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.H. Kim, J. Lim, J. Lee, D. Na, J. Shin, C. Kim, S. Yu, J. Shin, S. Lee, D. Rajagopal and 20 other author(s). ISSCC, page 1-3. IEEE, (2015)11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory.C. Kim, J. Cho, W. Jeong, I. Park, H. Park, D. Kim, D. Kang, S. Lee, J. Lee, W. Kim and 34 other author(s). ISSCC, page 202-203. IEEE, (2017)A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.J. Lee, D. Na, A. Kavala, H. Cho, J. Lee, M. Yang, E. Song, T. Kim, S. Lee, D. Jang and 16 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate.J. Im, W. Jeong, D. Kim, S. Nam, D. Shim, M. Choi, H. Yoon, D. Kim, Y. Kim, H. Park and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.K. Park, S. Nam, D. Kim, P. Kwak, D. Lee, Y. Choi, M. Choi, D. Kwak, D. Kim, M. Kim and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.D. Kim, H. Kim, S. Yun, Y. Song, J. Kim, S. Joe, K. Kang, J. Jang, H. Yoon, K. Lee and 35 other author(s). ISSCC, page 218-220. IEEE, (2020)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory.C. Kim, D. Kim, W. Jeong, H. Kim, I. Park, H. Park, J. Lee, J. Park, Y. Ahn, J. Lee and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)

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Disambiguation of "Byeon, Dae-Seok"

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7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.

Please choose a person to relate this publication to

Wonmin Byeon

Boseon Byeon

In-Deok Seok

Joon-Weon Seok

Dae-Ho Cho

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Byeon, Dae-Seok"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.

Please choose a person to relate this publication to

Wonmin Byeon

Boseon Byeon

In-Deok Seok

Joon-Weon Seok

Dae-Ho Cho

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.