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Disambiguation of "Mantovani, Paolo"

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Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study.

, , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2011)

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Mauro Mantovani

Dario Mantovani

Giordano Paolo

Nadine Didier-Mantovani

Paolo Molteni

 

Other publications of authors with the same name

Opinion: Why science needs philosophy, , , , , , , , and . Proceedings of the National Academy of Sciences, 116 (10): 3948--3952 (2019)Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study., , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2011)High-level synthesis of accelerators in embedded scalable platforms., , and . ASP-DAC, page 204-211. IEEE, (2016)A synchronous latency-insensitive RISC for better than worst-case design., and . Integr., (2015)Runtime reconfigurable memory hierarchy in embedded scalable platforms., , and . ASP-DAC, page 719-726. ACM, (2019)A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI., , , , , , and . IEEE J. Solid State Circuits, 47 (8): 1935-1945 (2012)Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP., , , and . CoRR, (2022)On maximal intermediate predicate constructive logics., , , and . Stud Logica, 57 (2/3): 373-408 (1996)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems., , , , , , and . DAC, page 157:1-157:6. ACM, (2016)