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Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.

, , и . Asian Test Symposium, стр. 94-99. IEEE Computer Society, (1996)

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Kozo Yabuta

Asako Kinoshita

Asako Kinoshita

Kozo Kosugi

Yvette Kozova-Razanantoanina

 

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Design of High-Level Test Language for Digital LSI., , и . ITC, стр. 508-513. IEEE Computer Society, (1983)Cascade Realization of 3-Input 3-Output Conservative Logic Circuits., и . IEEE Trans. Computers, 27 (3): 214-221 (1978)Realization of Minimum Circuits with Two-Input Conservative Logic Elements., и . IEEE Trans. Computers, 27 (8): 749-752 (1978)Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults., , и . FTCS, стр. 263-270. IEEE Computer Society, (1992)Extended selection of switching target faults in CONT algorithm for test generation., и . J. Electron. Test., 1 (3): 183-189 (1990)SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2561-2567 (2013)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , и . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Design of testing circuit and test generation for built-in current testing., , и . Syst. Comput. Jpn., 24 (5): 73-82 (1993)A BIST Circuit for IDDQ Tests., , , , , и . Asian Test Symposium, стр. 390-395. IEEE Computer Society, (2003)Memory reduction of IDDQ test compaction for internal and external bridging faults., и . Asian Test Symposium, стр. 350-355. IEEE Computer Society, (2000)