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A dynamically scheduled architecture for the synthesis of graph methods.

M. Minutoli, V. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. Hot Chips Symposium, page 1-7. IEEE, (2016)

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Johannes Marcour

Monika Marcotty

Hans-Ernst Marcolin

Carlos Javier Marcos Navas

Massimiliano Marcon

Other publications of authors with the same name

Bridging Python to Silicon: The SODA Toolchain.N. Agostini, S. Curzel, J. Zhang, A. Limaye, C. Tan, V. Amatya, M. Minutoli, V. Castellana, J. Manzano, D. Brooks and 2 other author(s). IEEE Micro, 42 (5): 78-88 (2022)Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators.S. Curzel, N. Agostini, S. Song, I. Dagli, A. Limaye, C. Tan, M. Minutoli, V. Castellana, V. Amatya, J. Manzano and 3 other author(s). ICCAD, page 1-7. IEEE, (2021)Practical Distributed Programming in C++.M. Drocco, V. Castellana, and M. Minutoli. HPDC, page 35-39. ACM, (2020)Productive Programming of Distributed Systems with the SHAD C++ Library.V. Castellana, and M. Minutoli. HPDC, page 263-264. ACM, (2021)High-Level Synthesis of Irregular Applications: A Case Study on Influence Maximization.R. Neff, M. Minutoli, A. Tumeo, and M. Becchi. CF, page 12-22. ACM, (2023)Scalable and Memory-Efficient Algorithms for Controlling Networked Epidemic Processes Using Multiplicative Weights Update Method.P. Sambaturu, M. Minutoli, M. Halappanavar, A. Kalyanaraman, and A. Vullikanti. IJCAI, page 5164-5170. ijcai.org, (2022)Invited: Software Defined Accelerators From Learning Tools Environment.A. Tumeo, M. Minutoli, V. Castellana, J. Manzano, V. Amatya, D. Brooks, and G. Wei. DAC, page 1-6. IEEE, (2020)OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays.C. Tan, N. Agostini, J. Zhang, M. Minutoli, V. Castellana, C. Xie, T. Geng, A. Li, K. Barker, and A. Tumeo. ASAP, page 149-155. IEEE, (2021)A dynamically scheduled architecture for the synthesis of graph methods.M. Minutoli, V. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. Hot Chips Symposium, page 1-7. IEEE, (2016)SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators.M. Minutoli, V. Castellana, C. Tan, J. Manzano, V. Amatya, A. Tumeo, D. Brooks, and G. Wei. ICCAD, page 98:1-98:7. IEEE, (2020)

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Disambiguation of "Minutoli, Marco"

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A dynamically scheduled architecture for the synthesis of graph methods.

Please choose a person to relate this publication to

Johannes Marcour

Monika Marcotty

Hans-Ernst Marcolin

Carlos Javier Marcos Navas

Massimiliano Marcon

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Minutoli, Marco"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A dynamically scheduled architecture for the synthesis of graph methods.

Please choose a person to relate this publication to

Johannes Marcour

Monika Marcotty

Hans-Ernst Marcolin

Carlos Javier Marcos Navas

Massimiliano Marcon

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A dynamically scheduled architecture for the synthesis of graph methods.