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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , и . ICICDT, стр. 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , и . ICICDT, стр. 1-4. IEEE, (2015)Computer Modeling of Silicon Quantum Dot Floating -Gate Flash Memory Devices. University of Illinois Urbana-Champaign, USA, (2001)NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures., , , , , , , , , и . IRPS, стр. 2. IEEE, (2015)FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below., , , , и . ICICDT, стр. 1-4. IEEE, (2015)Area and routing efficiency of SWD circuits compared to advanced CMOS., , , , , , , , и . ICICDT, стр. 1-4. IEEE, (2015)Holisitic device exploration for 7nm node., , , , , , , , , и 5 other автор(ы). CICC, стр. 1-5. IEEE, (2015)Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs., , , , , , , , , и 1 other автор(ы). ESSDERC, стр. 330-333. IEEE, (2012)Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , и . ESSDERC, стр. 412-415. IEEE, (2016)System-level assessment and area evaluation of Spin Wave logic circuits., , , , , , , и . NANOARCH, стр. 25-30. IEEE Computer Society/ACM, (2014)