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Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.

, , , , , , , и . ASYNC, стр. 80-. IEEE Computer Society, (1998)

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Saray Shai

Shai Haim

Shai Halevi

Faisal Karim Shaikh

Md Aftab Ali Shaikh

 

Другие публикации лиц с тем же именем

Relative timing asynchronous design., , и . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 129-140 (2003)Relative Timing., , и . ASYNC, стр. 208-218. IEEE Computer Society, (1999)RAPPID: An Asynchronous Instruction Length Decoder., , , , , , , , , и . ASYNC, стр. 60-70. IEEE Computer Society, (1999)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , и . ASYNC, стр. 62-72. IEEE Computer Society, (2000)CAD Directions for High Performance Asynchronous Circuits., , , , , , и . DAC, стр. 116-121. ACM Press, (1999)Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits., , , , , , , и . ASYNC, стр. 80-. IEEE Computer Society, (1998)Coordinated transformations for high-level synthesis of high performance microprocessor blocks., , , , , , , и . DAC, стр. 898-903. ACM, (2002)An asynchronous instruction length decoder., , , , , , , , и . IEEE J. Solid State Circuits, 36 (2): 217-228 (2001)