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Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs., , , , , , , , , and . ISLPED, page 15:1-15:6. ACM, (2022)MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration., , , , , , , , and . CoRR, (2021)Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (12): 1896-1904 (December 2023)On Legalization of Die Bonding Bumps and Pads for 3D ICs., , , , and . ISPD, page 62-70. ACM, (2023)Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs., , , , , , , and . ISLPED, page 1-6. IEEE, (2021)Thermal Performance Analysis of Mempool RISC-V Multicore SoC., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1668-1676 (2022)Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs., , , , , , , , , and 1 other author(s). 3DIC, page 1-4. IEEE, (2023)Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)., , , , , , , , , and 6 other author(s). IRPS, page 1-7. IEEE, (2023)MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration., , , , , , , , and . DATE, page 394-399. IEEE, (2022)