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Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input., , and . ASP-DAC, page 775-780. IEEE, (2009)On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.. J. Electron. Test., 22 (4-6): 387-398 (2006)LPTest: a Flexible Low-Power Test Pattern Generator., , and . J. Electron. Test., 25 (6): 323-335 (2009)Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (9): 553-566 (2003)A SAR ADC missing-decision level detection and removal technique., , , and . VTS, page 31-36. IEEE Computer Society, (2012)An Efficient Peak Power Reduction Technique for Scan Testing., , and . ATS, page 111-114. IEEE, (2007)BDD-Based Self-Test Program Generation for Processor Cores., , , and . ITC-Asia, page 1-6. IEEE, (2023)Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors., , , , and . ITC-Asia, page 1-6. IEEE, (2021)A scalable quantitative measure of IR-drop effects for scan pattern generation., , , , , and . ICCAD, page 162-167. IEEE, (2010)Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test., , , and . VTS, page 237-246. IEEE Computer Society, (2000)