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A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction.

T. Hsu, Y. Chen, R. Liu, C. Lo, K. Tang, M. Chang, и C. Hsieh. IEEE J. Solid State Circuits, 56 (5): 1588-1596 (2021)

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Chung-Chuan Chen

Jen-Yang Chuang

Shih-yu Chuang

Mei-Ling Chuang

Jing-Jing Chuang

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Diverse Community Structures in the Neuronal-Level Connectome of the Drosophila Brain.C. Shih, Y. Lin, C. Wang, T. Wang, C. Chen, T. Su, C. Lo, и A. Chiang. Neuroinformatics, 18 (2): 267-281 (2020)Estimating Sensorimotor Mapping From Stimuli to Behaviors to Infer C. elegans Movements by Neural Transmission Ability Through Connectome Databases.C. Li, C. Lo, и B. Chen. IEEE Trans. Neural Networks Learn. Syst., 27 (11): 2229-2241 (2016)POPPINS : A Population-Based Digital Spiking Neuromorphic Processor with Integer Quadratic Integrate-and-Fire Neurons.Z. Yeh, C. Hsu, A. White, C. Yeh, W. Wu, C. Wang, C. Lo, и K. Tang. CoRR, (2022)POPPINS: A Population-Based Digital Spiking Neuromorphic Processor with Integer Quadratic Integrate-and-Fire Neurons.Z. Yeh, C. Hsu, C. Yeh, W. Wu, C. Wang, C. Lo, и K. Tang. ISCAS, стр. 1-5. IEEE, (2021)Neuromorphic luminance-edge contextual preprocessing of naturally obscured targets.A. White, C. Hung, A. Harrison, и C. Lo. ICONS, стр. 36:1-36:8. ACM, (2023)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.J. Su, P. Lu, P. Wu, Y. Chou, T. Liu, Y. Chung, L. Hung, J. Ren, W. Huang, C. Chien и 11 other автор(ы). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (апреля 2024)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.C. Xue, T. Huang, J. Liu, T. Chang, H. Kao, J. Wang, T. Liu, S. Wei, S. Huang, W. Wei и 10 other автор(ы). ISSCC, стр. 244-246. IEEE, (2020)8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.J. Hung, T. Wen, Y. Huang, S. Huang, F. Chang, C. Su, W. Khwa, C. Lo, R. Liu, C. Hsieh и 4 other автор(ы). IEEE J. Solid State Circuits, 58 (1): 303-315 (2023)A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hong, J. Ren, T. Pan и 15 other автор(ы). IEEE J. Solid State Circuits, 58 (3): 877-892 (марта 2023)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou и 11 other автор(ы). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)

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