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An asynchronous instruction length decoder.

, , , , , , , , и . IEEE J. Solid State Circuits, 36 (2): 217-228 (2001)

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Jochen Marly

Marly Antonia Maldaner Jacobi

 

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Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy., и . Asynchronous Design Methodologies, том A-28 из IFIP Transactions, стр. 13-27. North-Holland, (1993)Modular Timing Constraints for Delay-Insensitive Systems., , , , и . J. Comput. Sci. Technol., 31 (1): 77-106 (2016)Fsimac: a fault simulator for asynchronous sequential circuits., , , , и . Asian Test Symposium, стр. 114-119. IEEE Computer Society, (2000)RAPPID: An Asynchronous Instruction Length Decoder., , , , , , , , , и . ASYNC, стр. 60-70. IEEE Computer Society, (1999)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , и . ASYNC, стр. 62-72. IEEE Computer Society, (2000)A Proof System for Brinch Hansen's Distributed Processes., , и . GI Jahrestagung, том 50 из Informatik-Fachberichte, стр. 88-95. Springer, (1981)CAD Directions for High Performance Asynchronous Circuits., , , , , , и . DAC, стр. 116-121. ACM Press, (1999)Naturalized Communication and Testing., , , , , и . ASYNC, стр. 77-84. IEEE Computer Society, (2015)Data-Loop-Free Self-Timed Circuit Verification., , , , и . ASYNC, стр. 51-58. IEEE Computer Society, (2018)A Framework for Asynchronous Circuit Modeling and Verification in ACL2., , , и . Haifa Verification Conference, том 10629 из Lecture Notes in Computer Science, стр. 3-18. Springer, (2017)