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Efficient Online and Offline Testing of Embedded DRAMs., , , , and . IEEE Trans. Computers, 51 (7): 801-809 (2002)Efficient fault simulation on many-core processors., , , and . DAC, page 380-385. ACM, (2010)The design of random-testable sequential circuits.. FTCS, page 110-117. IEEE Computer Society, (1989)Application of Deterministic Logic BIST on Industrial Circuits., , , and . J. Electron. Test., 17 (3-4): 351-362 (2001)Minimized Power Consumption for Scan-Based BIST., and . J. Electron. Test., 16 (3): 203-212 (2000)Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen, , , , and . VDI-Buch Springer Berlin Heidelberg, Berlin, Heidelberg, (2009)A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems., , , , , , and . J. Electron. Test., 30 (4): 401-413 (2014)Identifying Resistive Open Defects in Embedded Cells under Variations., and . J. Electron. Test., 39 (1): 27-40 (February 2023)Introduction., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 397-398 (2003)Panel Summaries., and . IEEE Des. Test Comput., 21 (1): 65-66 (2004)