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Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.

L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, and N. Badereddine. DDECS, page 353-358. IEEE Computer Society, (2011)

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Nabil Allam

Nabil Aboulkhair

Nabil Motosh

Nabil Irshaid

Nabil Sayed

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Detecting NBTI induced failures in SRAM core-cells.R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, and N. Badereddine. VTS, page 75-80. IEEE Computer Society, (2010)On the Test and Mitigation of Malfunctions in Low-Power SRAMs.L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Virazel, and N. Badereddine. J. Electron. Test., 30 (5): 611-627 (2014)Test solution for data retention faults in low-power SRAMs.L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, and N. Badereddine. DATE, page 442-447. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A statistical simulation method for reliability analysis of SRAM core-cells.R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, and N. Badereddine. DAC, page 853-856. ACM, (2010)Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, and N. Badereddine. DTIS, page 39-44. IEEE, (2013)Impact of Resistive-Bridging Defects in SRAM Core-Cell.R. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, and N. Badereddine. DELTA, page 265-269. IEEE Computer Society, (2010)Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, and N. Badereddine. ETS, page 1-6. IEEE Computer Society, (2013)Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, and H. Wunderlich. VLSI-SoC, page 403-408. IEEE, (2006)Power-Aware Test Data Compression for Embedded IP Cores.N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, S. Pravossoudovitch, and C. Landrault. ATS, page 5-10. IEEE, (2006)Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, and N. Badereddine. DDECS, page 353-358. IEEE Computer Society, (2011)

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Disambiguation of "Badereddine, Nabil"

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Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.

Please choose a person to relate this publication to

Nabil Allam

Nabil Aboulkhair

Nabil Motosh

Nabil Irshaid

Nabil Sayed

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Badereddine, Nabil"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.

Please choose a person to relate this publication to

Nabil Allam

Nabil Aboulkhair

Nabil Motosh

Nabil Irshaid

Nabil Sayed

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.