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Operation-aware assist circuit design for improved write performance of FinFET based SRAM., , , и . VDAT, стр. 1-6. IEEE, (2014)A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design., и . CSSP, 37 (2): 475-499 (2018)An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\) 32-bit Register File., и . CSSP, 36 (12): 4789-4808 (2017)High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell., , и . Wireless Personal Communications, 78 (1): 57-68 (2014)A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate., , и . ISED, стр. 151-153. IEEE, (2012)Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology., , , , и . Circuits and Systems, 2 (4): 326-329 (2011)Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits., и . J. Low Power Electron., 10 (1): 45-52 (2014)An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture., , , и . VLSID, стр. 133-138. IEEE, (2023)Novel Ultra Low Leakage FinFET Based SRAM Cell., , и . iNIS, стр. 89-92. IEEE, (2016)Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology., , и . iNIS, стр. 234-237. IEEE, (2017)