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pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang, S. Shin, H. Park, S. Park, Y. Choi, H. Lee, K. Jeon, J. Lee, H. Ahn, K. Kim, J. Kim, S. Chang, H. Hwang, D. Kim, Y. Yoon, S. Hyun, J. Park, Y. Song, Y. Park, H. Kwon, S. Bae, T. Oh, I. Song, Y. Bae, J. Choi, K. Park, S. Jang, and G. Jin. ISSCC, page 390-391. IEEE, (2017)

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Yong-Cheol Kim

Yong Cheol Lim

Puangrat Yongvanit

Li Yong

Karn Yongsiriwit

Other publications of authors with the same name

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.C. Lee, M. Ahn, D. Moon, K. Kim, Y. Eom, W. Lee, J. Kim, S. Yoon, B. Choi, S. Kwon and 6 other author(s). VLSIC, page 182-. IEEE, (2015)A mixed PLL/DLL architecture for low jitter clock generation.Y. Bae, and G. Wei. ISCAS (4), page 788-791. IEEE, (2004)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme.Y. Bae, J. Park, S. Rhee, S. Ko, Y. Jeong, K. Noh, Y. Son, J. Youn, Y. Chu, H. Cho and 9 other author(s). ISSCC, page 44-46. IEEE, (2012)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).H. Lee, S. Kang, H. Yu, W. Yun, J. Jung, S. Ahn, W. Kim, B. Kil, Y. Sung, S. Shin and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)

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Disambiguation of "Bae, Yong-Cheol"

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Yong-Cheol Kim

Yong Cheol Lim

Puangrat Yongvanit

Li Yong

Karn Yongsiriwit

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bae, Yong-Cheol"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.

Please choose a person to relate this publication to

Yong-Cheol Kim

Yong Cheol Lim

Puangrat Yongvanit

Li Yong

Karn Yongsiriwit

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.